A 1K pull up resistor is used to pull the signal wire IO Wire high. Because the DSA can function between 2. In order to shorten the time to market and keep up with the development of the market, you need a complete integration from the chip to the supply chain.
Maxim Integrated can provide you with integrated solutions in the industrial, medical, consumer, automotive, energy, computing and communications fields. The BC is an NPN bipolar junction transistor that can be used in many general purpose applications. Hello everyone! I hope you all are fine today. Today, we will have a discussion about UC UC is a current mode PWM controller.
This article mainly introduce pinout, datasheet, uses and other detailed information about On Semiconductor UC Also known as 2SC, the C is a bipolar junction NPN transistor widely used in commercial and educational projects. Account Center 0 Items. Utmel uses cookies to help deliver a better online experience. You can see what cookies we serve and how to set your preferences in our Cookies Policy , if you agree on our use of cookies please click continue.
Christmas and the New year Activity Details Christmas and the New year is coming, Utmel wants give you more support on your components order. How to get the discount coupon? Can enjoy the free charge of freight and discount together? How to have the discount for the off-line order? On the other hand, as shown in FIG. Since the sense amplifier operation is not completed, the voltage level of a sense node of the sense amplifier circuit rises due to the electrical charge flowing in from the parasitic capacitance of the write data line.
In such a case, as shown in FIG. This problem of inversion of data occurs in a sense amplifier circuit, particularly when the contact resistance value contact at a sense node to a bit line of a transistor in the sense amplifier circuit varies due to process variation since the sensing margin is smaller.
The fact that a column select operation cannot be started until the sensing operation is completed in order not to destruct the data means that a column-related operation cannot be started for until a long period after a bank activation command a row access command is dispatched. Moreover, even when a data read is performed for the same address after a mask write operation for instance, a write verified read , no data read is performed under the voltage level of the bit line is raised due to an electrical charge injection from a write data line during the mask write operation, so that data can be read accurately.
Thus, in the array arrangement shown in FIG. Sub-word line driver SWD is arranged in a sub-word line driver disposing region SWDR, and is shared by two memory cell blocks adjacent to one another in the row direction. In the hierarchical word line arrangement, a sub-word line driver is provided corresponding to a respective sub-word line, and a main word line is disposed to a corresponding to a prescribed number of sub-word lines.
Each sub-word line driver drives a corresponding sub-word according to at least the signal potential on the corresponding main word line. In this case, an arrangement may be used in which a sub-word line driver drives a corresponding sub-word line to the selected state according to a signal on a main word line and a sub-word line selecting signal when multiple sub-word lines are provided corresponding to one main word line.
In sub-word line driver disposing region SWDR, a sub-word line driver is disposed, but no memory cell nor sense amplifier circuit is arranged. A sense power supply line for transmitting sense amplifier power supply voltage VccS and ground voltage Vss is provided in this free region of the memory cell block, in the same layer as the read data bus and the write data bus or in an upper layer, to supply sense power supply voltage stably to each sense amplifier circuit.
Thus, this write driver operates statically according to internal write data WDD. CMOS inverters 26 a and 27 b operate using the voltage having the same voltage level as sense power supply voltage VccS as the operation power supply voltage. No problem arises even when using such a two-value driving write driver, as described below with reference to FIG.
The original purpose of the equalizing operation is to prevent the writing of uncertain data by transmission of the potential difference between the write data lines to the sense amplifier circuit while the write driver is in the output high impedance state.
Thus, there is no need for an equalizing operation, and no problem arises even when the write data lines are two-value driven. On the other hand, write column select signal CSLW has its amplitude set at external power supply voltage level, and is changed between ground voltage Vss and external power supply voltage Vcc. When data write is not performed, write column select line CSLW is in the inactive state, and transfer gates TGa and TGb are in the non-conductive state.
Thus, in these states, sense amplifier circuit SA is disconnected from write driver WDV or the spare write driver. Now, as seen in FIG. In such a case, the voltage of a gate of transfer gate TMa in write gate WG is at sense power supply voltage VccS level, i. After a signal having a lower voltage level than 2. If the threshold voltage of transfer gate TMa is greater than 0. Thus, transfer gate TMa has its gate and its source interconnected, and attains a state equivalent to a PN diode so that it becomes non-conductive.
In this case, although transfer gate TMb is in the conductive state, the two voltage levels are the same, and no through current flow is caused. Therefore, a data write is stably performed by driving a write driver with external power supply voltage Vcc. This power supply configuration is utilized in the first embodiment or the second embodiment. Power supply voltage VccS from voltage down converter VDC is also utilized as power supply voltage for driving a sense amplifier circuit inside a memory cell array MA.
A decode circuit XYD for selecting a memory cell in memory cell array MA is provided with an external power supply voltage Vcc 2 and a boosted voltage Vpp from a boosting circuit BST for boosting external power supply voltage Vccl.
Boosted voltage Vpp is used to drive a word line. External power supply voltage Vcc 2 is for example 2. In write driver group WDG, however, write drivers are provided for each memory cell array, and the total of bits of write drivers operate simultaneously. When power supply voltage VccS from voltage down converter circuit VDC is utilized, in the data write operation, sense power supply voltage VccS may be significantly lowered so that an accurate data write cannot be performed i.
Although the sense amplifier circuit consumes a large amount of current during this operation, as far as the power supply voltage becomes stable within a prescribed period, the sense amplifier circuit can sense and amplify memory cell data by accurate sensing operation. Thus, the response speed of voltage down converter VDC is relatively slowed, and it is possible that the drop in power supply voltage VccS cannot be sufficiently compensated for during the write operation of the write driver group.
Consequently, as shown in FIG. A circuit contained in data path DP operates according to external power supply voltage Vcc 2. A write driver group also operates according to external power supply voltage Vcc 2. Other parts of the power supply layout configuration is the same as those shown in FIG.
More specifically, when sense power supply voltage VccS is utilized, sense power supply voltage VccS is generated from external power supply voltage Vcc 1 , and the current is provided from external power supply voltage Vcc 1. If the amplitude of a signal line is 2. On the other hand, when the write data line is driven using only external power supply voltage Vcc 2 , consumed power would be proportional to 2.
Thus, power consumption is lower when only external power supply voltage Vcc 2 is used to drive the write data line. Flip-flop 33 outputs output data PAO of a preamplifier circuit. CMOS inverter latch circuit 32 operates using external power supply voltage Vcc for example, 2.
With the use of read data line isolating gate 31 , the load on a sense node can be alleviated during the sensing and amplifying operation of CMOS inverter latch circuit 32 so that the sensing and amplifying operation can be performed at a high-speed.
By utilizing an external power supply voltage in a preamplifier, the power consumed during the preamplifier operation is reduced and the sense amplifier power supply is kept from being reduced. As seen from the above, according to the second embodiment of the present invention, since a write gate is formed of a transfer gate receiving at its gate a data mask signal and a transfer gate receiving a write column select signal connected in series, the load for the write driver is alleviated and a high-speed data write becomes possible.
Moreover, by utilizing a bi-state buffer as a write driver, the precharging period of the write data line is no longer required, and a shorter write cycle time is achieved. Further, by utilizing external power supply voltage Vcc as a power supply voltage for a write driver, the malfunctioning of the sense amplifier circuit and of the write driver due to the lowered sense amplifier power supply voltage, can be prevented, so that data write can be performed accurately, and power consumption can be reduced.
Sense amplifier circuit SA operates using as an operation power supply voltage, and drives one of sense nodes SNa and SNb to the level of sense amplifier power supply voltage VccS. With the arrangement shown in FIG. Even when external power supply voltage Vcc is set at a voltage of, for example, 1. At this time, the voltage levels of the write data lines, however, are the same, and sense amplifier circuit SA holds the data stably if the sense amplifying operation is completed.
In addition, even before the completion of the sensing operation, the external power supply voltage is near the bit line precharge voltage level 1. When external power supply voltage Vcc is low, i. AND circuit AG operates using. Therefore, as in the case described above, a voltage lower than sense amplifier power supply voltage VccS can be used as operation power supply voltage Vcc for the write driver to perform a data write operation.
Thus, the time for precharging a write data line is no longer required. In addition, power consumption can be reduced due to the use of a lower external power supply voltage Vcc. AND circuit AG is arranged in the free region where a sense amplifier band intersects a sub-word line decoders, for instance, so that the increase in the array area can be limited while a write column select signal at sense amplifier power supply voltage VccS can be transmitted to each write gate WG.
As seen from the above, according to the third embodiment of the present invention, since a column select signal is driven to the sense amplifier power supply voltage level, the power supply voltage of a write driver can be set at an external power supply voltage level lower than the sense amplifier power supply voltage, thereby significantly reducing power consumption. An AND circuit for receiving the data mask signal and the sense amplifier activating signal to generate a local data mask signal is arranged in the portion where a sub-word line driver group SWDG disposing region intersects a sense amplifier group disposing region.
Each of these AND circuits 40 a to 40 f receives sense amplifier power supply voltage VccS as one operation power supply voltage. Moreover, local data mask signals from these AND circuits 40 a to 40 f are provided to write gates 64 write gates corresponding to 8-bit write data line pairs IOW arranged for the corresponding sense amplifier groups.
In a column access, a column is accessed for data writing in the row block in the active state. Therefore, column access is not performed for memory cell blocks MBa and MBb in this case. DM latch 8 operates using sense amplifier power supply voltage VccS as one operation power supply voltage. Now, consider the operation in which a row block including a memory cell block MCB 1 is in the selected state, and a column selection for memory cell block MCB 1 is to be performed.
Here, only the one-page operation is considered. Thus, in the arrangement shown in FIG. Further, although AND circuits 40 - 0 to 40 - 17 respectively operate using sense amplifier power supply voltage VccS as one operation power supply voltage as shown in FIG.
Moreover, DM latch 8 is not required to drive data mask signal lines arranged for all row blocks but required to drive a global data mask line in the column direction only, so that the data mask signal can be set to the definite state at a high speed. Furthermore, in a two-page mode operation, two row blocks are selected, and a sense amplifier activating signal for the two row blocks is driven to the active state. Although the column select operation is performed for one row block, the data mask signal, therefore, is required to drive local data mask lines for these two activated row blocks.
External power supply voltage Vcc is utilized as the operation power supply voltage for DM latch 8 shown in parentheses in FIG.
In this arrangement, the provision of a level converting function to AND circuits 40 - 0 to 40 - 19 can cope with the situation where the voltage level of external power supply voltage Vcc is lower than sense amplifier power supply voltage VccS. Consequently, even when a data mask signal is a positive logic signal, a data mask signal transmission line can be divided into a global mask data line and a local data mask line.
Thus, in the similar manner, the data mask signal can be driven to the definite state, and in conjunction with the arrangement utilizing a bi-state buffer as a write driver, the write operation can be performed at a high speed and with low current consumption.
In an arrangement in which the write data is masked for each eight IO data line pairs as shown in FIG. Moreover, a write driver can be implemented as a bi-state driver, and there is no need for a precharging operation of an internal write data line. Application of this configuration provided with such a write mask gate to different data bit widths is now considered.
For simplicity, FIG. In each of sense blocks SB 0 to SB 3 , eight sense amplifier circuits are arranged for each IO data line pair so that the total of sixty-four sense amplifier circuits are provided. Eight sense amplifier circuits form one sense amplifier unit, as will be described below.
Each of column select blocks CSB 0 to CSB 3 selects eight sense amplifier circuits from a corresponding one of sense blocks SB 0 to SB 3 according to column select signal CSLG on the column select line group and couples the eight sense amplifier circuits to the corresponding 8-bit IO data line pairs. Each of write mask circuits WM 0 to WM 3 inhibits the data write operation with eight IO data line pairs being a unit, as in the previous first embodiment.
IO data line pairs IO 0 to IO 31 are internal data line pairs for transmitting both write data and read data. For simplicity, no preamplifier circuit is shown in the figure.
Data line selecting signals YD 0 to YD 3 are generated according to a column address signal corresponding to the write data bit width. Moreover, the correspondence between write mask instruction applied from an outside and internal mask instructions DMa to DMd is changed according to the write data bit width. When the input data bit width is changed, the connections between these write drivers WDV 0 to WDV 31 and data input circuits are changed individually per write driver group corresponding to each of write mask circuits WM 0 to WM 3.
Consequently, the connection of a non-selected IO data line pair to a sense block is inhibited so that transmission of the precharge voltage of the IO data lines to sense blocks SB 0 to SB 3 is prevented, and the write data can be accurately written into a selected memory cell even when the input data bit width is changed.
Thus, in the configuration shown in FIG. One group of IO data line pairs is selected according to internal data line selecting signals YD 0 to YD 3 and the data write operation is performed. The arrangements of other parts are the same as those shown in FIG. Now, an operation of a write circuit shown in FIG. Therefore, by setting the connections between data input circuit and write driver in the unit of each of write mask circuits WM 0 to WM 3 , write mask circuit for a non-selected write driver block is set to the non-conductive state so that the connection of a precharged IO data line pair to a sense amplifier circuit can be prevented, and thus, change in data held by a sense amplifier circuit can be prevented.
At time td, the write operation is completed. In the write driver enable signal generating portion shown in FIG. The arrangements of other parts is the same as those shown in FIG. Only the write driver enable signals for a selected IO data line pair group is activated. When no defective IO data line exist in the group of IO data line pairs selected by internal data line selecting signals YD 0 to YD 3 , an output signal from switching circuit SX attains the high impedance state.
In this case, spare write data WDS from spare multiplexer SMUX should be set to the logic state of setting the corresponding spare write driver to the output high impedance state.
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